Many integrated circuit devices include at least one embedded core and external circuitry that provides inputs to and accepts outputs from the embedded core. The embedded core commonly has a plurality of inputs and outputs. It is advantageous to be able to isolate the embedded core from the external logic for core manufacturing testing, and to isolate the external logic from the embedded core for external logic manufacturing testing. Scan isolation feedback testing can be used to test the core separately from the external logic, and scan isolation bypass testing can be used to test the external circuitry separately from the core. However, scan isolation feedback and bypass testing can be difficult to implement without impacting the silicon area of the integrated circuit device.
Current scan isolation and bypass architectures may require the addition of a state element and a multiplexer for each of the inputs and outputs of the embedded core. This additional circuitry can require a large amount of silicon area on the die, especially when the core has a large number of input and output pins.
It would be desirable to have a scan isolation feedback and bypass architecture that does not need a state element for each input and output of the target core and that uses less silicon area for the scan isolation feedback and bypass circuitry, even when the target core has a large number of inputs and outputs.